Interconnect scaling in nanometer CMOS technologies leads to capacitive coupling between adjacent signal lines as well as reduces noise margin. Furthermore, increase in operating temperature results in increase in interconnect resistance and decrease in drive strength of transistors, hence a small crosstalk pulse that is not harmful at nominal temperature may reach sufficient size for propagation through downstream logic due to temperature effects. This work examines the effect of temperature on crosstalk noise (TICN) in 22 nm CMOS interconnects based on a distributed \(6\)–\(\pi\) RC model and HSPICE simulation based on Predictive Technology Model devices. In particular, the proposed solution includes the temperature-controlled transmission-gate suppression circuit where the biases on PMOS and NMOS gates are provided by PTAT and CTAT voltages. Generated biases allow tuning the effective conductance of the transmission gate so that temperature-increased crosstalk pulses get attenuated before they reach the victim receiver threshold. Extensive simulations involving more than 500 cases with different values of interconnect length, coupling length, aggressor and victim strengths reveal average reduction of TICN of about 96%. In addition, complete cancellation of TICN occurs in 87% of examined cases without resizing of aggressor/victim drivers.
